Generally, the high integration of a Dynamic Random Access Memory (DRAM) has been achieved through the development of semiconductor device fabrication equipment and processing technology, design techniques, memory cell structure, etc.
There have been, however, many problems in developing highly integrated memory devices due to the physically imposed limitations of the semiconductor fabrication equipment and semiconductor device itself.
For example, in order to achieve a highly integrated memory device there should be a decreased area for the storage capacitor. In addition to the above matter, a decrease in area of a Metal Oxide Semiconductor (hereinafter, referred to as "MOS") device should also be followed.
In semiconductor devices with integration greater than the VLSI level, the elements in one MOS device should have the effective channel length within a range of 0.5 .mu.m and should secure a predetermined interval between the conductors because of the narrowed interval between devices due to the increased integration. The increase in integration is inevitably followed by the problem of the shorting of the conductors, etc.
Especially, in semiconductor device with Ultra Large Scale Integration over 256 Megabit DRAM, technology is needed for forming a contact hole capable of securing an alignment margin for maintaining the insulation of the conductors, because the width between the word lines and the width between the bit lines are as narrow as a minimum line width.
The following is a description in detail of a prior art process for forming the contact of the bit line and storage node referring to FIG. 1 and 2.
FIG. 1 is a plan view of a common DRAM. It shows multiple parallel word lines and multiple parallel bit lines orthogonal to the word line. The bit line contact and storage node contact are positioned at the portions of intersection where the bit line intersect with the word lines, and are respectively, electrically connected with the drain and source. As shown in FIG. 1, the bit line contacts are denoted as "BT" and the storage node contacts as "ST".
In addition, the interval between the word lines is denoted as "A", the width of the bit line as "B", and the interval between the bit lines as "C", respectively.
FIG. 2 is a sectional view taken along X-X' line in FIG. 1, which illustrates a method for fabricating a DRAM cell according to the conventional art.
First referring to FIG. 2A, a silicon dioxide layer 17, approximately 350 Angstroms thick, is thermally grown on a silicon substrate 1.
Typically, the substrate would be a relatively large wafer which after processing would be cut up into a number of chips. Each of the chips would include a VLSI circuit employing a large number of p-channel and n-channel transistors. A polycrystalline silicon (hereinafter, referred to as "polysilicon") layer with a thickness of 4500 .ANG. is formed on the silicon dioxide layer by low pressure chemical vapor deposition (LPCVD).
Predetermined portions of the deposited polysilicon layer and the silicon dioxide layer are selectively removed, using a conventional photolithographic and etching process (the first masking step) to form the gate patterns of 2 and 17 shown in FIG. 2A.
After the process of establishing the gate patterns, p(Boron) and n(Phosphorous or Arsenic) type impurities are implanted into the exposed portions of the substrate with doses sufficient for forming p and n diffusion regions of the source and drain. The implanted impurities are then thermally diffused by a thermal anneal process. Through the above processes, as shown in FIG. 2A, a MOS transistor structure is formed.
In the MOS device, drain and source regions are electrically connected with the bit line or the storage node electrode via contact holes formed at an insulating layer which is to be formed on the MOS structure of FIG. 2A through succeeding process steps. Hereinafter, for the sake of illustration, diffused portions in electrical contact with bit line contact are referred to as "drain" and diffused portions in contact with storage node contact are referred to as "source".
Turning now to FIG. 2B, after the formation of the diffusion layer, the first insulating layer 3 is deposited on the entire surface of the resultant MOS structure. The purpose of the deposition is to deposit an insulating layer 3 with a planar surface and thereby alleviating the height difference between the gate region and the source and the drain region.
Second and third layers 5 and 6, are deposited on the first insulating layer 3 sequentially, in which the etching rate of each layer is sufficiently different from one another. The second layer 5 has a higher etching rate than the third layer 6.
Referring now to FIG. 2C, the second and third insulating layers are selectively etched away by an anisotropic etch using a mask pattern, to define a ring-shaped contact hole due to the difference of the two layers in the etch rate. Hereinafter, we refer the ring-shaped pattern etched by difference in etch rate to as the "T-shaped pattern" for the sake of convenience. In FIG. 2C, a head portion and a leg portion of the T-shaped pattern are denoted as 6' and 5' respectively.
Sidewall polysilicon spacers 9 and 9' are then formed by depositing a polysilicon layer on the T-shaped insulating layer pattern and etching the polysilicon layer anisotropically. On the entire surface of the resultant structure after the formation of the polysilicon pattern, a fourth insulating layer 7 is deposited to form a plane surface resulting in the profile shown in FIG. 2D.
Next, a photoresist mask pattern (not shown in drawings) is formed on the fourth insulating layer 7 exposing a predetermined surface of the fourth insulating layer over the heads of the T-shaped insulating patterns. The predetermined portion of the fourth insulating layer 7 and T-shaped insulating layers are etched away by means of the pattern of the photoresist mask with the inside face pattern of the sidewall polysilicon spacer 9 acting as an etch barrier. And, continuously, a portion of the first insulating layer 3 wherein the leg of the T-shaped insulating layer pattern is downwardly extended, is etched away until the diffusion layer is exposed. A contact hole 20 is formed by the above etch process as shown in FIG. 2E.
A conductive layer of polysilicon, for example, is then deposited at the entire surface including the contact hole 20 by chemical vapor deposition and patterned to provide a contact 12 of the bit line by extending through the contact hole 20 to the surface of the drain region 22, as shown in FIG. 2F.
After the formation of the contact 12, a fifth insulating layer 10 is deposited on the entire surface of the resultant semiconductor structure. A mask pattern 15 is then formed on the fifth insulating layer 10 to provide a contact hole for a storage node electrode. Using the mask pattern, predetermined portions of the fifth insulating layer 10, the fourth insulating layer 7 and the T-shaped insulating layer (the third and second insulating layer) inside the sidewall polysilicon spacers 9', are etched away anisoptropically. Simultaneously, the portion of the first insulating layer 3 where the leg of the T-shaped insulating layer pattern is downwardly extended, is etched away until the doped source region is exposed. A contact hole 21 is formed by the above etch process as shown in FIG. 2G.
FIG. 3 is a sectional view of DRAM cell according to the conventional art illustrated in FIG. 2 and is sectioned along the Y-Y' line of FIG. 1.
First we can compare FIG. 1 with FIG. 2G in order to grasp a problem in the conventional fabrication process of semiconductor device. In accordance with FIG. 2, it seems that there is no problem at the bit line contact portions and the storage node contact portions sectioned in parallel with the bit lines (BL.sub.1, BL.sub.2, BL.sub.3).
However, by comparing FIG. 1 with FIG. 3, an important problem is shown in the storage node contact portions: the head portion of T-shaped storage node contact is aligned with bit lines BL.sub.1 and BL.sub.2. The result is that the bit lines BL.sub.1 and BL.sub.2 are in direct contact with the storage node electrode so that semiconductor device manufactured by conventional process always has a shorting problem.